"
The Adventure Vision
is a cartridge based, electronic hand held video game that was
manufactured in 1982 by Entex Industries, Inc. The system measures
about 13 1/4" X 10" X 9" and uses one vertical strip of 40 red
LEDs and a spinning mirror to produce an apparent screen resolution of
150x40 (drawn at 15 frames/sec). While there are only four
cartridges
for this system, those four games are all arcade classics, Defender,
Turtles, Super Cobra, and an Asteroids clone, Space Force."
Actual photos taken by compiling and running the core here
Content
This project recreates all of the circuits found in Entex' Adventure
Vision handheld video game including CPU and audio/video generation.
Here is a detailed list of internal components:
- Intel 8048
CPU - T48
core from opencores.org
Copyright (c) 2004-2006 Arnim Laeuger (arniml at opencores.org)
- National COP411L Sound CPU - T400 core from opencores.org
Copyright (c) 2006 Arnim Laeuger (arniml at opencores.org)
- Display controller for 40 LED strip
- General purpose I/O for controller
- Clock generator - operates with main 11 MHz clock (external
or PLL)
- Reset generator - requires power-on reset capability of FPGA
External components are:
- BIOS ROM - 1 kByte
- CPU RAM - 1 kByte
- Cartridge ROM - up to 4 kByte
- Framebuffer and rasterizer to convert the display information to
VGA and RGB monitors
- RGB DACs
Download the latest version 1.1 of the FPGA Adventure Vision project
here:
fpga_adventurevision_1.1.tar.gz
Note, on Windows machines you may have to save the ZIP file before you
can open it. Make sure the extension is .tar.gz
It contains two fully functional system toplevels for
Simple Solution's Zefant
XS3-1000 on the Mini-ITX board (Xilinx Spartan3 1000) and the
Cyclone Board by
JOP.design (Altera Cyclone
EP1C12).
Resource Usage
Following is the flow summary for an Altera Cyclone device:
+-------------------------------------------------------------------+
; Flow
Summary
;
+-------------------------+-----------------------------------------+
; Flow
Status
; Successful - Sat May 13 16:57:19 2006 ;
; Quartus II Version ; 6.0 Build 178
04/27/2006 SJ Web Edition ;
; Revision
Name ;
jop_av
;
; Top-level Entity Name ;
jop_av
;
;
Family
;
Cyclone
;
;
Device
;
EP1C12Q240C8
;
; Timing
Models ;
Final
;
; Met timing requirements ;
Yes
;
; Total logic elements ; 1,657 / 12,060 ( 14 %
)
;
; Total
pins
; 139 / 173 ( 80 %
)
;
; Total virtual pins ;
0
;
; Total memory bits ; 37,504 /
239,616 ( 16 %
)
;
; Total
PLLs
; 1 / 2 ( 50 %
)
;
+-------------------------+-----------------------------------------+
Fitting results for a Spartan3 1000 (XC3S1000FG456):
Please note that this design contains additional logic
and RAM for the scan doubler.
Logic Utilization:
Total Number Slice
Registers: 886 out of
15,360 5%
Number used as Flip
Flops:
885
Number used as
Latches:
1
Number of 4 input
LUTs: 2,313
out of 15,360 15%
Logic Distribution:
Number of occupied
Slices:
1,421 out of 7,680 18%
Number of Slices containing only related
logic: 1,421 out of 1,421 100%
Number of Slices containing unrelated
logic: 0 out
of 1,421 0%
*See NOTES below for an explanation of
the effects of unrelated logic
Total Number 4 input
LUTs: 2,430 out
of 15,360 15%
Number used as
logic:
2,313
Number used as a
route-thru: 71
Number used for Dual Port
RAMs: 44
(Two LUTs used per Dual Port RAM)
Number used as Shift
registers: 2
Number of bonded
IOBs:
255 out of 333 76%
IOB Flip
Flops:
24
Number of Block
RAMs:
9 out of 24 37%
Number of
GCLKs:
3 out of 8 37%
Number of
DCMs:
1 out of 4 25%
Total equivalent gate count for design: 622,816
Legal Issues
Redistribution and use in source and synthesized forms, with or without
modification, are permitted provided that the following conditions are
met:
Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
Redistributions in synthesized form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
Neither the name of the author nor the names of other contributors may
be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
See also the file COPYING.
Please note:
The copyright of the ROM images is owned by third parties, thus the
above does not apply to them. You have to be entitled separately to use
the ROM images together with the FPGA Adventure Vision design. Owning
an
original Adventure Vision console and the cartridges might be ok, but I
am
not liable for any
copyright
violations that arise from your use of the FPGA Adventure Vision design.
I will ignore any requests for a copy of the ROM images.
References
--
Arnim Läuger
<arnim.laeuger at gmx.net>
