library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;

entity TEST is
  port (
    PIN_1_IN     : in    std_logic;
    PIN_1_OUT    : out   std_logic;
    PIN_2_IN     : in    std_logic;
    PIN_2_OUT    : out   std_logic;
    PIN_3        : out   std_logic;
    PIN_4        : out   std_logic;
    PIN_5        : out   std_logic;
    PIN_6        : out   std_logic;
    PIN_7        : out   std_logic;
    PIN_8        : out   std_logic;
    PIN_9        : out   std_logic;
    PIN_10       : out   std_logic;
    PIN_11       : out   std_logic;
    PIN_12       : out   std_logic;
    PIN_13       : out   std_logic;
  --PIN_14       GND

    PIN_15       : out   std_logic;
    PIN_16       : out   std_logic;
    PIN_17       : out   std_logic;
    PIN_18       : out   std_logic;
    PIN_19       : out   std_logic;
    PIN_20       : out   std_logic;
    PIN_21       : out   std_logic;
    PIN_22       : out   std_logic;
    PIN_23       : out   std_logic;
    PIN_24       : out   std_logic;
    PIN_25       : out   std_logic;
    PIN_26       : out   std_logic;
    PIN_27       : out   std_logic;
  --PIN_28       VCC

    SP_GND1      : out   std_logic;
    SP_GND2      : out   std_logic

    );
end;

architecture RTL of TEST is
  signal clk : std_logic;
  signal counter : std_logic_vector(26 downto 0);
  signal led : std_logic_vector(24 downto 0);
begin
  clk <= PIN_1_IN;
  PIN_1_OUT <= 'Z';

  PIN_2_OUT <= led(0);
  --PIN_2_OUT <= 'Z';

  PIN_3  <= led(1);
  PIN_4  <= led(2);
  PIN_5  <= led(3);
  PIN_6  <= led(4);
  PIN_7  <= led(5);
  PIN_8  <= led(6);
  PIN_9  <= led(7);
  PIN_10 <= led(8);
  PIN_11 <= led(9);
  PIN_12 <= led(10);
  PIN_13 <= led(11);

  PIN_15 <= led(12);
  PIN_16 <= led(13);
  PIN_17 <= led(14);
  PIN_18 <= led(15);
  PIN_19 <= led(16);
  PIN_20 <= led(17);
  PIN_21 <= led(18);
  PIN_22 <= led(19);
  PIN_23 <= led(20);
  PIN_24 <= led(21);
  PIN_25 <= led(22);
  PIN_26 <= led(23);
  PIN_27 <= led(24);

  SP_GND1 <= '0';
  SP_GND2 <= '0';

  p_counter : process
  begin
    wait until rising_edge(clk);
    counter <= counter + "1";
  end process;

  p_leds : process
  begin
    wait until rising_edge(clk);
    if (counter(26) = '0') then
      case counter(23 downto 22) is
        when "00" => led <= "1000100010001000100010001";
        when "01" => led <= "0100010001000100010001000";
        when "10" => led <= "0010001000100010001000100";
        when "11" => led <= "0001000100010001000100010";
        when others => null;
      end case;
    else
      case counter(23 downto 22) is
        when "00" => led <= "1111111111111111111111111";
        when "01" => led <= "0000000000000000000000000";
        when "10" => led <= "1111111111111111111111111";
        when "11" => led <= "0000000000000000000000000";
        when others => null;
      end case;
    end if;
  end process;

end RTL;