Actual photos taken by compiling and running the code here
Contents
This project recreates most of the circuits found on the
original PCBs of the Philips VIDEOPAC G7000 and Magnavox Odyssey
2
consoles, including CPU, RAM, video and sound
generation.
Following is a detailed list of internal components:
- i8048 CPU - T48
core from opencores.org
Copyright (c) 2004-2007 Arnim Läuger (arniml at opencores.org)
Including 1 kByte BIOS ROM
- i8244 / i8245 Video Display Controller
Including 256 Byte characterset ROM
- 256 Byte RAM
- General purpose I/O for controller
- Clock generator - operates with main 21.5 MHz (NTSC) or
35.5 MHz
(PAL) clock (external
or PLL)
- Reset generator - requires power-on reset capability of FPGA
External components are:
- Cartridge ROM - up to 16 kByte
- Optional software driven multicart controller
- PS/2 keyboard interface logic by John Clayton and John Kent
- RGB DACs
- Audio DAC
Download the latest version 1.0 of the FPGA Videopac project here:
fpga_videopac-1.0.tar.gz
Note, on Windows machines you may have to save the ZIP file before you
can open it. Make sure the extension is .tar.gz
It contains two fully functional system toplevels for
Simple Solution's Zefant
XS3-1000 on the Mini-ITX board (Xilinx Spartan3 1000) and the
Cyclone Board by
JOP.design (Altera Cyclone
EP1C12).
Resource Usage
Following is the flow summary for an Altera Cyclone device:
+------------------------------------------------------------------+
; Flow
Summary
;
+-------------------------+----------------------------------------+
; Flow
Status
; Successful - Thu Apr 05 23:40:29 2007 ;
; Quartus II Version ; 7.0 Build 33
02/05/2007 SJ Web Edition ;
; Revision
Name ;
jop_vp
;
; Top-level Entity Name ;
jop_vp
;
;
Family
;
Cyclone
;
;
Device
;
EP1C12Q240C8
;
; Timing
Models ;
Final
;
; Met timing requirements ;
N/A
;
; Total logic elements ; 3,503 / 12,060 ( 29 %
)
;
; Total
pins
; 139 / 173 ( 80 %
)
;
; Total virtual pins ;
0
;
; Total memory bits ; 79,360 /
239,616 ( 33 %
)
;
; Total
PLLs
; 1 / 2 ( 50 %
)
;
+-------------------------+----------------------------------------+
Fitting results for a Spartan3 1000 (XC3S1000FG456):
Please note that this design contains additional logic
for the AC97 controller and additional RAM for the scan doubler.
Logic Utilization:
Total Number Slice Registers: 2,015 out
of 15,360 13%
Number used as Flip
Flops:
2,014
Number used as
Latches:
1
Number of 4 input
LUTs: 3,930
out of 15,360 25%
Logic Distribution:
Number of occupied
Slices:
2,964 out of 7,680 38%
Number of Slices containing only related
logic: 2,964 out of 2,964 100%
Number of Slices containing unrelated
logic: 0 out
of 2,964 0%
*See NOTES below for an explanation of
the effects of unrelated logic
Total Number of 4 input
LUTs: 4,079 out
of 15,360 26%
Number used as
logic:
3,930
Number used as a
route-thru: 92
Number used for Dual Port
RAMs: 52
(Two LUTs used per Dual Port RAM)
Number used as Shift
registers: 5
Number of bonded
IOBs:
255 out of 333 76%
IOB Flip
Flops:
48
Number of Block
RAMs:
6 out of 24 25%
Number of
GCLKs:
3 out of 8 37%
Number of
DCMs:
1 out of 4 25%
Total equivalent gate count for design: 446,903
Legal Issues
Redistribution and use in source and synthesized forms, with or without
modification, are permitted provided that the following conditions are
met:
Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
Redistributions in synthesized form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
Neither the name of the author nor the names of other contributors may
be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
See also the file COPYING.
Please note:
The copyright of the ROM images is owned by third parties, thus the
above does not apply to them. You have to be entitled separately to use
the ROM images together with the FPGA Videopac design. Owning an
original Videopac console and the cartridges might be ok, but I am
not liable for any
copyright
violations that arise from your use of the FPGA Videopac design.
I will ignore any requests for a copy of the ROM images.
References
Videopac G7000 / Odyssey
2:
i8048 & i8244:
--
Arnim Läuger
<arnim.laeuger at gmx.net>
